Timing Simulation problem

[blimp]

Hi,
I meet critical problems during the timing simulation after back-anotation.
Functional simulation is ok but when trying to do the timing simulation on Modelsim, most of the signals on Modesim are red colours I can see.

Who knows or experieces this? Although I try to solve this problem, I can't do that
I need somebody to help me to save the design time of my project.

 

[nand_gates]

Find out uninitialized flops in ur design initialize them to first '1' or '0' at the
begining of the simulation. If ur design contains memories replace them with
gate level model.

 

[haytham]

do you have any error messges of setup or hold time violations.
if you have then the synthesized circuit is not meeting the timing constraints. You need either to relax the clock or to analyze your negative slack paths and try to break them with DFFs.

Thanks
Haytham

 

[caplash_vlsi]

its a bit painful but very effective....wat u can do is that use the option of stepping from modelsim......that way u can check each n every statement being executed....and find bugs....also check for negative slacks in ur design and try breaknig the critical paths with flops inserted in between...............