Timing Simulation of ASIC Netlist

[grand]

Hi.

I have a Stabdard Cell Library description in Synopsys format (*.lib). Also I have a Verilog model of these cells with unit delay. As I noted, the *.lib file contains all necessary data of the timing characteristics of each cell.

For synthesis I use Leonardo Spectrum and Synplify ASIC.

So, my question is can I simulate the synthesed netlist with delays described in *.lib file? If YES - how?

 

[gnomix]

Yes you can!
I haven't worked with your synthesys tools but e.g. Synopsys can write the sdf file with the timing relative of your implementation.
Try to see, if in some menu, you can find an option to save the sdf file or the back-annotation file and use it with your simulation tool.

 

[sandusty]

Since you are using dc, would you please try the following command:

write_constraints -format sdf(or sdf-v2.1) -cover_design filename.sdf

make your gate level design and sdf to be the input of your simulator...

 

[balik]

You should extract sdf and use this sdf in simulation. Of course your verilog cell library has only unit delays but during sdf annotation simulator replace these delays by delays from sdf file.

 

[maniasonic]

be sure that you have add right constraints on your design before you write out your sdf file, or your sdf will not make sense.