Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Timing Report differences between Design Compiler and PT

Status
Not open for further replies.
V

vlsiwiz

Newbie level 4
Joined
Mar 28, 2007
Messages
7
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Location
USA
Activity points
1,323
Hello Everyone,

I'm seeing some differences between a timing report from DC and PT. The PT timing report is optimisitic. I've checked all conditions, and they seem to be identical for both tools. Any ideas on why this is happenning ?

Thanks!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top