timing path b/w different clocks

[Aimerbhat]

in DC ,i am try to get STA for the path b/w two flip flops which are clocked at clk and clkby 2 respectiveley . in report_timing ,It is showing no delay corresponding to the combinational logic cells in between these flip flops
I even tried various version on DC but wasnt able to get hold of the problem.
kindly help

regards
aimer

 

[Aimerbhat]

hi , i gt it
dc_shell kind of rounds off propogation delays if they are very small as compared to timing constraint of the path