timing optimization in soc encounter urgent

[lightcloud]

encounter reclaimarea

Hi,
I am doing timing optimization in soc encounter,now I have a few question:

1.After place, I optimize the timing.When I select setup and design rule option,
the final utilization change from 0.7 to 0.95,but in astro the utilization change
is limited in 5%,so I want to know how to control it?Maybe I select setup option
and after CTS I select design rule option.Did all design rule violation should be
fixed?
2.Does anyone know the timing optimization flow in soc encounter?
3.how to do buffer tree in soc encounter,such as reset signal,do it in CTS as clock
signal?

best regards

 

[p_shinde]

after detail routing, we check for any negative slack in setup time and then do timing optimization to remove them ...then comes CTS if not done earlier.. followed by hold time analysis...same thing is checked in hold time too i.e if there are any negative slacks , then run TO to remove it............

if we r not able to remove it by timing optimization... then how do we do it manually thats my Q...


let me know if anything is wrong....
thanks,
Prasad

 

[zhustudio]

1. I think you can view the detail report of your timing analysis. Do you use large buffer to fix the cap and transition violation. And do you use reclaim area option. If you use SOC5.2 you can this option is detault. It can shrink the cell size in none-critical path.

2. You can run optdesign after placement. And then CTS -> optdesign -> fix hold -> detail route -> optdesign post and fix(if necessary).

3. For buffer tree, I just let encounter automatic optimize design, it will add some buffer in the high fanout net.

 

[lightcloud]

Thanks,when I synthesis I used zero wire load model,maybe this affect the optimization?

 

[smith_kang]

Hi
In SoC Encounter Timing optimization can be done in
1. preCts stage (after Placement)
2. postCts stage (after CTS)
3. postRoute stage.
Utilization you can control. This means that you are contraining the tool to work on optimization.
In optmization itself the tool will check for DRV violations and try to fix it. No Not all the violations can be fixed. It will issue warning like How much real violations are there and how much it can fix.
I think in your design there is Huge negative slack and DRVs so to accomodate tool is trying to add more buffers.
Try to give reclaimArea option.

Hope it helps

 

[steven852]

I think your core utilization ratio is too high. Also check conjestion. If they are too high, try to repartition and region some blocks. Otherwise, you may think of enlarging the core.

Just my 2 cents.