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Timing delay and area information in Virtex FPGA

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lahrach

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Hi friends,

How can I use ISE 11.5 to analyze timing in Virtex-5 using ISE 11.5 kit, which tool can I use?
regards
 

You can use Timing analyzer.
 

Dear

I also am trying to figure this out... Well I know that Timing Analyzer will do that but I have somewhat similar question

for Lahrach: You can find timing analyzer at : program-> ISE -> ISE design tools -> tools -> Timing Analyzer
There you have to insert I gues .ncd file of your project to get the timing report... Rest I also want to know....:D


Gongdori... Can you elaborate how can we find the following

1) Critical time of our circuit
2) False paths (also if Mutli cycle, no idea if can or cannot)
3) maximum and minimum period for clock

I have seen the report many times... Generated my self but could not find the critical Path...

I think Critical path will decide out Minimum Time period for clock ( so 3 may be pointless). Any way there is
no heading or writing indicating critical path (path consuming greatest time)
 

When you open up the timing analyzer, you can run the analyzer by timing constraint. Also, you can set it up to display N worst timing paths.
Of course, the worst timing path is the bottle neck of the design.

A designer needs to specify false paths of the design. The tool does not know unless they are specified.
 

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