Timing constraints: Offset In and Offset Out

[fmaximovic]

Hello,

I'm working on a VHDL project using Xilinx ISE 14.1 and I'm facing some trouble with Timing Constraints.

As far as the Period constraint is asked there's no problem, I understand it; what's bugging me is how to choose the offset in and out constraints: I've never done it before and I don't know why I should care about those too.

So far I have tried randomly, reading what the Timing Report says (like "the minimum allowable offset in is...") and acting accordingly, but I'm not fully satisfied.

Any help?

 

[dftrtl]

When your design interacts with outside world we need to consider the Input and Output delay such that capture from outside into FPGA will happen properly and launch from FPGA get captured properly outside.
You need to give 70% of clock period as Input delay and 70% of clock period as output delay.

Let me know if you have still some questions.