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timing constraints - input to output path

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ee1

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Hi,
can anyone tell me how should i constraint a path from input to output - without any F.F between?...

thanks!
 

PL give a schematic diag. to explain your reqts .The case can be sorted out using opto couplers and current paths taken care of .However , the ckt design needs to be carefully studied in detail.
 

a diagram would certainly help..but how about set_max_delay/min_delay
 

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