Thanks for the reply. I shall go through the document.. Is it like for Vivado IPs, I don't need to bother about the timing constraints at all. If I write HDL code of my own, then how am i suppose to calculate the set up and hold times? Is set up and hold time applicable only for the design which is connected to the pins of the FPGA. What about the internal logic, will they also have set up and hold times? Where will find the values of set up and hold times for them?