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Timing constraints for design

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benhu

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I am doing project with about 4 modules which are driven by same clock 200 mhz ..I have idea about STA and about the delay concepts ..
I am not getting how to give timing constraints for the design for synthesis in design compiler ...
please anybody help me to just tell me how to proceed forward .
.I know to give clock ..
But for behavorial design how to give constraints ..I have specifications as
The default timing constraint values are:
• Point to point signals: — 40% output valid — 50% input setup — 10% spare slack
• Multiplexed signals: — 40% output valid — 20% multiplexer — 30% input setup
— 10% spare slack.
How to know multiplexed signals and point to point signals ..?

Clock skew needs to be set explicitly as minus (worst case) and plus (best case)
uncertainty. The following default values have been used as preliminary values prior to
layout:
• minus uncertainty is 5% of the clock period
• plus uncertainty is 40% of the minus uncertainty, which is 2% of the clock period.

So these all constraints must be given to overall design or wrt modules...?
 

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