Timing check on designs having XOR based frequency doubler

[jason-zyx]

In our project we have a PLL which outputs two clocks and they are XOR-ed to generate a clock with 2x higher frequency. When we do STA, we have problem because when creating generated clocks doubling clock isn't supported, so we can't get the delay from PLL and through the XOR gate propagated automatically.

Is there anyone who did this as well? Any good ideas and suggestions?

 

[lostinxlation]

Why don't you create(not generate) the clock at the output of the XOR ? Unless there are branches off on the clock between PLL and the XOR gates, the latency between PLL and XOR doesn't mean anything. Or defining a clock at only one of the PLL output is another way.

Other than that, such a clock doesn't guarantee x2 frequency and I'd look for some other way to generate x2 clock.

 

[jason-zyx]

The two clocks from the PLL are orthogonal, i.e. one of them is 90 degree away from another. So XOR-ing them will get a 2x clock w/ good (not perfect) duty cycle. If we don't do it this way, we would need a PLL w/ 4x VCO and devide it down by 2 to get a 50-50 clock. Then the PLL divide ratio is too high as the external reference is too low.

So we decided to use this XOR-ing approach, although it's challenging as a symmetrical gate is required and we have this STA issue. We care the latency between PLL and XOR because one of the PLL output (1x) is also used and the 2x and 1x need to be synchronous.

We found a way which is to define a 2x clock at the PLL output, and propogate it through the XOR. Just as you suggested. Thanks for the valuable input.