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Timing analysis guidance

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dayana42200

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Hi all.

Im using Xilinx ISE Design Suite 14.7 for my timing analysis using a constraint shown below.

NET "Clk" TNM_NET = "Clk";
TIMESPEC "TS_Clk" = PERIOD "Clk" 40 ns HIGH 50%;
OFFSET = IN 15 ns VALID 17 ns BEFORE Clk;
OFFSET = OUT 8 ns AFTER Clk;

After PAR there were errors on the timing analysis based on the timing constraint above. Below shows some of the error example

2018-12-22_8-46-20.jpg

I need help and guidance based on the experience to improve the timing issue.

Thank you very much.

- - - Updated - - -

I add some timing analysis details for slack no .1

2018-12-22_9-06-45.jpg
 

ads-ee

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10x the period you requested!?

Did you notice you have 632 levels of logic, there isn't a technology anywhere that can run at 25MHz with that many levels of logic.

You better show us your code you obviously didn't account for levels of logic between sequential elements anywhere in your code..
 

barry

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632 logic levels??? THAT sounds like a problem. I think you need some pipelining.

Oops, just saw Ads's post.
 

vGoodtimes

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There should be some pipeline register stages in the systolic array.
 

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