timin Violations................plz help

[santoshl]

Hi, All

I'm a fresh college grad into industry as front end design engineer in design Center.
Im currently doing synthesis and STA.

What are the different techniques to fix timing violations........especially setup violations?

Hope u will help me

Thanks in advance

Santosh L

 

[quan228228]

you have following methods:

1. set_critical_range
2. group_path
3. ungroup
4.set_flatten
5. modify RTL code

David

 

[santoshl]

Thanks for the information David

Will u plz explian in brief all the alternatives u mentioned. and im in post layout stage so which is more appropriate choice for me?

Thanks and regards
santosh l

 

[megastar007]

First four will be good at post layout stage

 

[shiv_emf]

setup violation at post layout stage ! Well be specific wht sort of error u r having !

 

[spauls]

upsizing wil help to some extent.

 

[Wenf.Yeh]

set time violation must be fixed in the pre-layout stage,or u would get a fail design!!
slightly hold time violation can be fixed in the post-layout stage.
best regards
Athur

 

[funzero]

if u have 10% timing violation, use synthesis approach, if you have more , redesign the violated part may be good

 

[santoshl]

Thanks everone
"if u have 10% timing violation, use synthesis approach, if you have more , redesign the violated part may be good"
as said by funzero
is tht 10% with respect to total number of paths?
or somethingf else

 

[avimit]

10% is the percentage of the timing by which your worst path is failing.
For example, if you are working on 100Mhz(i.e 10ns clock period), and your worst path is more than 11ns, which is 10ns(allowed) + 10% of 10ns
Kr,
Avi
http://www.vlsiip.com