That's true the simulator doesn't care about time resolution, but only if there's a single clock, and there are no delays modeled in your system (and you've done a perfect job using non-blocking assignments for sequential logic and regular blocking assignments with 0 delays for combinatorial logic). As soon as you have to deal with multiple clocks or other asynchronous stimulus, then you need a delays with a timescale to specify the relationships between when these events happen.
People do use simulation for timing analysis, although not as accurate as specific timing analysis tools. Many gate-level libraries have delays modeled in them.
And as soon as one part of your simulation ,either in your testbench or design, introduces a timescale with delays, then all of your design needs to deal with time as a single global variable with a common time resolution.