Timequest - finding the weakest link

[shaiko]

Hello,

Using the Altera's Time-quest timing analyzer, I found out that my design's Fmax on a particular FPGA is 372.22MHz (report Fmax summary).

How is it possible to see the "weakest link" in my design?
I.E - longest register to register time delay...

 

[K-J]

How is it possible to see the "weakest link" in my design?
I.E - longest register to register time delay...

In the Compilation Report, you should see the following (or something similar):
TimeQuest Timing Analyzer->Slow 1200mV 85C Model->Worst-Case Timing Paths->Setup: 'Clock'

Logic paths that fail timing are highlighted in red.

Kevin

 

[ads-ee]

Logic paths that fail timing are highlighted in red.

Kevin

And both of those that fail and don't fail are sorted according to the worst to the best, i.e. the weakest link to the strongest one.