time consumption by various modules and the testbench

[tariq786]

Can you help me in find out the amount of simulation time spent in testbench and the DUT?

Also is it possible to find out the % of simulation time spent in an individual module instance?

Lastly, how to find out the % of the simulation time spent in communication between two or more module instances?


Please let me know if you have any questions.

THanks

 

[rca]

Mentor quests tool as some feature to explore which modules consume the simulation time. I never tried, just seen that from mentor tech day.

 

[dave_59]

I think you mean to ask the amount of CPU time spent to execute code in a particular module or instance of a module. Look at Questa/Modelsim Profiling tools in the User Guide, or whatever tool you are using. Assuming your DUT is in one set of modules and your testbench is in another set of modules, the amount of CPU time spent for each should be easy to analyze.

The amount of time to communicate between modules is a difficult concept to define. The elaboration and optimization phases gets rid of much of the module hierarchy before simulation starts, And its difficult to distinguish the logic in a module that is only there to communicate with another module .

 

[tariq786]

I think you mean to ask the amount of CPU time spent to execute code in a particular module or instance of a module. Look at Questa/Modelsim Profiling tools in the User Guide, or whatever tool you are using. Assuming your DUT is in one set of modules and your testbench is in another set of modules, the amount of CPU time spent for each should be easy to analyze.

The amount of time to communicate between modules is a difficult concept to define. The elaboration and optimization phases gets rid of much of the module hierarchy before simulation starts, And its difficult to distinguish the logic in a module that is only there to communicate with another module .

Dave then how to find out the degree of parallelism in a design? I mean if module hierarchy is suppressed as much as possible then how can a designer know if he/she can successfully (with speedup > 1) run multi-core simulation on the design where one set of modules are simulated on one cpu core and the other set of modules is simulated on the second cpu core. Does that make sense?

Please let me know if you have any questions.

Thanks for your reply

 

[dave_59]

Dave then how to find out the degree of parallelism in a design? I mean if module hierarchy is suppressed as much as possible then how can a designer know if he/she can successfully (with speedup > 1) run multi-core simulation on the design where one set of modules are simulated on one cpu core and the other set of modules is simulated on the second cpu core.

This has been a area of great research for many decades with no clear results. It not really a problem of simply distributing the CPU resources; it is also scheduling the events in a proper order to minimize the amount of time each CPU is idle waiting for the results of another CPU.