Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
It is so difficult to answer this sort of questions, where it is not clear where the person asking this is coming from, what are the underlying assumptions, models, etc.
If the question is not straightforward, it is better to set the stage for the question - by explaining more about your problem.
What is the root cause of the voltage shift?
What are the time steps that you are talking about?
This seems to be something related to degradation or time-dependent (or history-dependent) variation of Vt...
Here is the answer - shift of Vt is given by this formula - dVt = dQ/C, where dQ is the change of charge over time (somewhere near the channel), and C is the capacitance (gate oxide plus some portion of the channel or depletion region). But the usefulness of this answer is about the same as the completeness of the question...
I wanted to know the process for calculating the threshold voltage shift in amorphous silicon thin film transistor using device simulator ATLAS SILVACO? I wanted to know the model that will be helpful for me and also the proper way to define step time??Kindly explain with some example based on simulation?