yefj
Advanced Member level 5
Hello, In a slide below taken from the manual they say that maximal common model is Vdd-Vsg3+Vt1
two questions:
1.the last step from drain of M1 and gate of M1 the voltage drop is Vt1 ,its the condition which M1 will stay saturated.
However in the table they say that Vd-Vg>=-Vth
Why there is a minus in the Vth but in table they use +Vth as the condition for M1 will stay saturated.
2.What is the meaning of absolute value in the PMOS saturation condition?
Thanks.
https://aicdesign.org/wp-content/uploads/2018/08/lecture19-150211.pdf
two questions:
1.the last step from drain of M1 and gate of M1 the voltage drop is Vt1 ,its the condition which M1 will stay saturated.
However in the table they say that Vd-Vg>=-Vth
Why there is a minus in the Vth but in table they use +Vth as the condition for M1 will stay saturated.
2.What is the meaning of absolute value in the PMOS saturation condition?
Thanks.
https://aicdesign.org/wp-content/uploads/2018/08/lecture19-150211.pdf