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Three questions about post-layout simulation

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Ruritania

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On postlayout simulation

Hi, the following two questions open to discussion, thanks.


(1). Is it indispensable to perform postlayout simulation for all of the analog circuits?

(2). I'm now using a 0.8um BiCMOS process to develop an anolog IC. While performing the postlayout simulation, I found that the parasitic of a contact (poly1 to metal1 or poly2 to metal1) is about 20ohm, is this normal? (This is much larger than I supposed)

(3). Is there anyone who has ever used ADS to perform postlayout simulation? I had some problem while importing the Hspice netlist.

Regards.
 

Ruritania

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Re: On postlayout simulation

sorry, they're 3 questions :p
 

sunking

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Re: On postlayout simulation

pay attention to the line value of W/L

if the frequency is not very high and the DC operation point is not very critical, 0.8u cmos is no need to do postlayout simulation
 

khorram

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Re: On postlayout simulation

I think you have to do post-layout simulation. Sometimes, your design passes the post-layout simulation, but after manufacturing it maybe have some problems and does not work. Therefore, perform post-layout simulation in all conditions.

(3). Is there anyone who has ever used @DS to perform postlayout simulation? I had some problem while importing the Hspice netlist.
Please expain the problem in details, maybe i can help you.

Regards,
KH
 

qslazio

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On postlayout simulation

(1) yes and it is very important for any practical ic (analog as well as digital)
(2) it is a little bit more than normal (several Ohm) you can add more contact and shorten your poly length(poly has more resistance)
(3) whether you are using @DS or Virtuoso , the netlist generated by them should always be modified to satisfied HSPICE syntax.
 

Colbhaidh

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Re: On postlayout simulation

Regarding (2):
Parasitic contact resistance between Poly and metal layers should be several 100 MOhms !! What process are you using?
 

purefen

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Re: On postlayout simulation

regarding (1):
the postsim can help u find out the parastic capacitance which u maybe not consider when u are in design phase. For high frequency application, it bring u some surprise. For example: oscillation frequency drift; overdamping on ac response that boost high frequency noise; unwated pole that degrade ur PM or GM; capacitance mismatch of filter make the f3dB drfit; suprising zero.....etc. .
 

Ruritania

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Re: On postlayout simulation

Thank you all for the opinions. Here's something to add on my questions.

(1). Some guys working at some analog design companies told me that they usually do not perform the postlayout simulation at all (they're designing power management chips and LCD driver chips). What they said did surprise me and that's why I posted the question here. I do not have much of experience on analog IC, but I think postlayout simulation may be necessary for developing good products.

(2). I have consulted some guys from the manufacturing companies about this question today. They all said that it is quite normal to have the contact of about 20 Ohm with the size of 1um*1um. Although I still think that the parasitic resistance is a little too big, but I accepted it now. And the suggestions from qslazio are very effective, that's what I'm gonna adpot in my design.

(3). I'm using xCalibre to extract my layout, the problem is that the extracted RC are up to several thousands, especially for the VDD and VSS runner. I'm wondering whether it is possible for ADS to "eat" so many device, and give out the right simulation results? (I'm doubting about this, coz the result was OK when I used Hspice to perform the simulation, while ADS gave no results at all )

PS: based on question 3, I'm wondering whether it is necessary or not to extract the parasitic RC for the power lines(VDD and VSS)?? and I wish I could get some advices on this issue, thank you.
 

Teddy

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Re: On postlayout simulation

Post layout simulation is good thing to do but it also depends on what you are doing.
Usually the extraction decs are focusing to RC constants so for DC_DC it does not have much sense (in my opinion)
20Ohm /contact sound pretty good to me.
In Calibre you should be able to set which nets you do not want to extract. Ask your CAD guy or call Mentor - MG usually helps more.
To extract VDD/VSS - again depends what you are doing and how the deck is written. Imagine measuring the resistance of the bus between the pad and structure itself. It could go really high hence affect performance of your circuit. It also affect ESD performance.
But you would have to limit amount of extracted data, decrease precision etc to be able to simulate it.
 

layes2

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Re: On postlayout simulation

high speed circuit
>500M
<0.35u
need post simulation
high performance circuit
also
 

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