Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 module adc_12b(clk,d_in,d_out,sclk,cs); input clk; //,reset; input d_in; output [11:0] d_out; output sclk,cs; reg cs; reg [11:0] temp; reg [1:0] state=2'b00, nxt_state; reg [4:0] count,count1; reg [11:0] dout; assign sclk=clk; parameter idle=2'b00, read=2'b01; // always@(posedge clk) // begin // if(reset) // state=idle; // else // state=nxt_state; // end always@(posedge clk) begin // if(reset) // count<=0; // else if(count>=5'd16) count<=0; else if(state==idle) begin count<=0; count<=count+1; end else count<=0; end always@(posedge clk) begin // if(reset) // count1<=0; // else if(count1>=5'd16) count1<=0; else if(state==read) count1<=count1+1; else count1<=0; end always @(negedge clk) begin case(state) idle:begin if (count==5'd16) begin nxt_state <= read; cs <= 1'd0; end else begin nxt_state <= idle; cs <= 1'd1; end end read:begin if(count1<=5'd16) begin temp[0] <= d_in; temp[1] <= temp[0]; temp[2] <= temp[1]; temp[3] <= temp[2]; temp[4] <= temp[3]; temp[5] <= temp[4]; temp[6] <= temp[5]; temp[7] <= temp[6]; temp[8] <= temp[7]; temp[9] <= temp[8]; temp[10] <= temp[9]; temp[11] <= temp[10]; nxt_state <= read; end else begin nxt_state <= idle; dout<=temp; end end endcase end assign d_out=dout; endmodule
Really you commented out the reset!?
Why?
FvM's suggestion to run a simulation will yield useless results as there will be X's everywhere as the FSM has no information on where to start.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 module adc_12b(clk,d_in,d_out,sclk,cs); input clk; //,reset; input d_in; output [11:0] d_out; output sclk,cs; reg cs; reg [11:0] temp; reg [1:0] state=2'b00, nxt_state; reg [4:0] count,count1; reg [11:0] dout; assign sclk=clk; parameter idle=2'b00, read=2'b01; // always@(posedge clk) // begin // if(reset) // state=idle; // else // state=nxt_state; // end always@(posedge clk) begin // if(reset) // count<=0; // else if(count>=5'd16) count<=0; else if(state==idle) begin count<=0; count<=count+1; end else count<=0; end always@(posedge clk) begin // if(reset) // count1<=0; // else if(count1>=5'd16) count1<=0; else if(state==read) count1<=count1+1; else count1<=0; end always @(negedge clk) begin case(state) idle:begin if (count==5'd16) begin nxt_state <= read; cs <= 1'd0; end else begin nxt_state <= idle; cs <= 1'd1; end end read:begin if(count1<=5'd16) begin temp[0] <= d_in; temp[1] <= temp[0]; temp[2] <= temp[1]; temp[3] <= temp[2]; temp[4] <= temp[3]; temp[5] <= temp[4]; temp[6] <= temp[5]; temp[7] <= temp[6]; temp[8] <= temp[7]; temp[9] <= temp[8]; temp[10] <= temp[9]; temp[11] <= temp[10]; nxt_state <= read; end else begin nxt_state <= idle; dout<=temp; end end endcase end assign d_out=dout; endmodule
the timing diagram is as below
View attachment 146646
Really you commented out the reset!?
Why?
FvM's suggestion to run a simulation will yield useless results as there will be X's everywhere as the FSM has no information on where to start.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 module adc_new1(clk,d_in,,ch,d_out,sclk,cs); input clk; input d_in; output ch; output [15:0] d_out; output sclk,cs; wire cs; reg [15:0] temp; reg [1:0] state=2'b00; reg [4:0] count=0; reg [4:0]count1=0; reg [15:0] dout; reg ch=0; assign sclk=clk; parameter idle=2'b00, read=2'b01; assign cs = 1'd0; // always@(posedge clk) // begin // if(reset) // state=idle; // else // state=nxt_state; // end always@(posedge clk) begin // if(reset) // count<=0; // else if(count>5'd3) count<=0; else if(state==idle) begin //count<=0; count<=count+1; end else count<=0; end always@(posedge clk) begin // if(reset) // count1<=0; // else if(count1>5'd15) count1<=0; else if(state==read) count1<=count1+1; else count1<=0; end always @(posedge clk) begin case(state) idle:begin if (count==5'd15) begin state <= read; //cs <= 1'd0; end else begin state <= idle; //cs <= 1'd1; end end read:begin if(count1<=5'd15) begin temp[0] <= d_in; temp[1] <= temp[0]; temp[2] <= temp[1]; temp[3] <= temp[2]; temp[4] <= temp[3]; temp[5] <= temp[4]; temp[6] <= temp[5]; temp[7] <= temp[6]; temp[8] <= temp[7]; temp[9] <= temp[8]; temp[10] <= temp[9]; temp[11] <= temp[10]; temp[12] <= temp[11]; temp[13] <= temp[12]; temp[14] <= temp[13]; temp[15] <= temp[14]; state <= read; end else begin state <= idle; dout<=temp; end end endcase end assign d_out=dout; endmodule
CS is not operated in the latest code, can't work.
- - - Updated - - -
Additional points, you never mentioned the clock frequency driving your design. Consider that ADC122S101 must keep an SCLK range of 8 to 16 MHz. I see that you have been playing around with clock edges. It's correct to read DOUT at the rising edge of SCLK, to comply with the datasheet specification, CS (and also DIN, if utilized) must be set at the falling SCLK edge.
The best way to achieve it is to clock the design at double SCLK frequency and toggle SCLK in your design.
module adc_new1(clk,d_in,,ch,d_out,sclk,cs);
input clk;
input d_in;
output ch;
output [11:0] d_out;
output sclk,cs;
reg cs;
reg [11:0] temp;
reg [1:0] state=2'b00;
reg [4:0] count=0,count1=0;
reg [11:0] dout;
reg ch=0;
assign sclk=clk;
parameter idle=2'b00, read=2'b01;
// always@(posedge clk)
// begin
// if(reset)
// state=idle;
// else
// state=nxt_state;
// end
always@(posedge clk)
begin
// if(reset)
// count<=0;
// else
if(count>=5'd16)
count<=0;
else if(state==idle)
begin
count<=0;
count<=count+1;
end
else
count<=0;
end
always@(posedge clk)
begin
// if(reset)
// count1<=0;
// else
if(count1>=5'd16)
count1<=0;
else if(state==read)
count1<=count1+1;
else
count1<=0;
end
always @(negedge clk)
begin
case(state)
idle:begin
if (count==5'd16)
begin
state <= read;
cs <= 1'd0;
end
else
begin
state <= idle;
cs <= 1'd1;
end
end
read:begin
if(count1<5'd16)
begin
temp[0] <= d_in;
temp[1] <= temp[0];
temp[2] <= temp[1];
temp[3] <= temp[2];
temp[4] <= temp[3];
temp[5] <= temp[4];
temp[6] <= temp[5];
temp[7] <= temp[6];
temp[8] <= temp[7];
temp[9] <= temp[8];
temp[10] <= temp[9];
temp[11] <= temp[10];
state <= read;
end
else
begin
state <= idle;
dout<=temp;
end
end
endcase
end
assign d_out=dout;
endmodule
clk: is only in the FPGA, thus it is not meantioned in the datasheetIn the timing diagram also they didnt mentioned about the clock frequency.
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