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thin oxide cover substrate contact

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fanshuo

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I was asked to cover the substrate contact with thin oxide which also cover the body of transistor
anybody know why to do it?

ThX
 

Top oxide layer dopped with phosphorus commonly known as P-Glass is used as device passivation layer. This protect device from corrosion.
 
I was asked to cover the substrate contact with thin oxide which also cover the body of transistor

Thin oxide = gate oxide is exclusively to be used for the gates. Substrate contact = NMOS body contact needs metal1 over it. Any oxide between would prevent the contact.
 
Active (thin ox) is also a hard mask (along w/ poly) for N+/P+ implant.
 

I was asked to cover the substrate contact with thin oxide which also cover the body of transistor
anybody know why to do it?

ThX

Are you talking about drawn layers in a layout tools or something else?

If so, is 'thin oxide' the name of the layer or is the layer used something called 'RX' or "ACT' or 'DIFF'?
 

what I mean is when doing layout
you have the layer called thinox(thin oxide)

you will found it cover the body of NMOS/PMOS

why should I cover the NMOS/PMOS together with its body contact with one thinox?
what is the advange
 

You get to save several overlaps and spacings if you use a common
active (tox) region. Lay out two versions, and see.
 

what I mean is when doing layout
you have the layer called thinox(thin oxide)

you will found it cover the body of NMOS/PMOS

why should I cover the NMOS/PMOS together with its body contact with one thinox?
what is the advange

what do you mean by "body of NMOS/PMOS": the whole FET (including gate, source and drain) or the body/bulk contact?

I have gone through a few foundries by now and this is a first, who are you using?

since this problem is very specific to your foundry/PDK, you should probably describe which layers you had to use to build your FETs (an NMOS would suffice) so we can understand if your thinox layer is just a thinox layer (a layer that most foundries do not use - usually only the thick oxide layers are used and every FET not using thick oxide is assumed thin) OR if it is an RX/Diffusion layer which is used by most foundries and has multiple purposes
 
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There is no reason to cover body contacts with Oxide layers.
As already stated, the layer affected by Thin/Med/Thick layers is Poly only.
If you have dataprep manual you can easily double check.
 

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