abhishektyagi
Newbie level 5
Hello Everyone,
I have access to Arm® Artisan® 7nm TSMC CLN07FF41001 Single-Port Ultra-High-Density SRAM Compiler. I have been able to get it to run on my system.
My aim is to do a Power and Area analysis of different SRAM configurations. To do so, I am trying to understand the workflow of the memory compiler. I know that the memory compiler can generate different views which can be used with several EDA tools.
I would appreciate if anyone can point me in the right direction here with respect to what sort of view I should be looking at and use it with an EDA tool. Any inputs would be appreciated
I have access to Arm® Artisan® 7nm TSMC CLN07FF41001 Single-Port Ultra-High-Density SRAM Compiler. I have been able to get it to run on my system.
My aim is to do a Power and Area analysis of different SRAM configurations. To do so, I am trying to understand the workflow of the memory compiler. I know that the memory compiler can generate different views which can be used with several EDA tools.
I would appreciate if anyone can point me in the right direction here with respect to what sort of view I should be looking at and use it with an EDA tool. Any inputs would be appreciated