Nov 24, 2013 #1 S shaiko Advanced Member level 5 Joined Aug 20, 2011 Messages 2,644 Helped 303 Reputation 608 Reaction score 297 Trophy points 1,363 Activity points 18,302 What does the VHDL "EXT" function do? How is it different from the "resize" function?
Nov 24, 2013 #2 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 The main difference is SXT/EXT are for std_logic_vectors. Resize is for signed/unsigned types. SXT/EXT are non-standard VHDL EXT zero extends the std_logic_vector. SXT sign extends. EXT and SXT are both from the non-standard package std_logic_arith. resize always extends based on type (so unsigned is zero extended, signed is sign extended).
The main difference is SXT/EXT are for std_logic_vectors. Resize is for signed/unsigned types. SXT/EXT are non-standard VHDL EXT zero extends the std_logic_vector. SXT sign extends. EXT and SXT are both from the non-standard package std_logic_arith. resize always extends based on type (so unsigned is zero extended, signed is sign extended).