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No idea. Maybe the FINFET is just a crappy FET (as early
developmental devices often are). Maybe you should step
back, look at some properly biased individual device DC I-V
curves (maybe against some known-good regular FETs) and
be sure the FINFET is actually useful, not just interesting.
And of course looking at real data is an opportunity not to
be missed, if you can find some.
After all, what could possibly go wrong with a FET that has
four interfaces instead of one, and is a 3-D instead of 2-D
problem?
A single curve's worth of data is worth more than any further
conjecture. If you have these papers perhaps there is some
way for you to sanity-check the pmos model result.
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