The sigma-delta ADC architecture

[kuohsi]

sigma delta adc architecture

I have studied the sigma-delta ADC theory, decide to use single loop architecture.
What is the modulator advantage and disadvantage between feedback and feedforward single loop architecture?
Thanks for your reply!

 

[arunkumar446]

feed back ->stability problems , some times we have to add zeros to make it stable, it becomes complex if it goes beyond 2,3 or so.
feed forward-> no need to worry about stability but have to decide the scaling parameters according to the voltage levelts at input and output of integrators even this is same for feed back one.

 

[kuohsi]

feed back ->stability problems , some times we have to add zeros to make it stable, it becomes complex if it goes beyond 2,3 or so.
feed forward-> no need to worry about stability but have to decide the scaling parameters according to the voltage levelts at input and output of integrators even this is same for feed back one.

Thanks for your reply!
But are they inverse??
feed back-->shall be stable due to feedback theory!
feedforward-->maybe unstall.
Are the postion inverse?
Thanks a lot!

 

[arunkumar446]

if we go to higher order sigma delta modulators single loop architectures become unstable as the order increases. so we go for MASH which is stable which is kind of like cascade or some thing like that.

 

[kuohsi]

if we go to higher order sigma delta modulators single loop architectures become unstable as the order increases. so we go for MASH which is stable which is kind of like cascade or some thing like that.

Thank you very much!arunkumar446!
Can I ask one question?
Why does feed-forward have to decide the scaling parameters according to the voltage levelts at input and output of integrators??

 

[arunkumar446]

if the scaling factors are not chosen properly the integrator outputs may go beyond the saturation values of the opamps used to realize the integrators. so scaling facture fix this.

 

[kuohsi]

if the scaling factors are not chosen properly the integrator outputs may go beyond the saturation values of the opamps used to realize the integrators. so scaling facture fix this.

Thank you very much!arunkumar446!
Can I ask another question?
If I scale the factor, the Vin doesn't go to full scale value??
(i.e. Vin < Vref ? If Vin can not equal Vref?)
Thank you very much!

 

[santom]

Yes..The Vin value should be kept lower when compared to the Vref value.May be 0.25*Vref would be better to have the proper scaling.

Also the 1 bit or 1.5 bits (output level which u choose) can only be acheived by having the scaling process in this way.

 

[kuohsi]

Yes..The Vin value should be kept lower when compared to the Vref value.May be 0.25*Vref would be better to have the proper scaling.

Also the 1 bit or 1.5 bits (output level which u choose) can only be acheived by having the scaling process in this way.

Thank you,santom!
Can I ask a question?
The Vin < 0.25*Vref

If I design a 16-bit ADC, I only have output value 65535*0.25 (0.25*Vref)=16383?
so I have output value only form 0~16383? Is it right?
Thank you!

 

[karim365]

if we go to higher order sigma delta modulators single loop architectures become unstable as the order increases. so we go for MASH which is stable which is kind of like cascade or some thing like that.

Thank you very much!arunkumar446!
Can I ask one question?
Why does feed-forward have to decide the scaling parameters according to the voltage levelts at input and output of integrators??