[SOLVED] The Risk of Having No ESD Protection. To be ESDed or NOT, this is a question.

[powerofthedream]

Dear Friends,

Just recently found out an issue about the ESD protection when designing a transmitter with about 20 pins, the 8GHz centre frequency RF signal's output waveform has been really twisted after adding the ESD protection circuitry, I suppose this is due to the parasitic or something else. Could I just remove the output ESD protection, and keep the other pins' ESD ?

The chip is supposed to be wrapped in the QFN package after the fabrication. As I heard, the un-ESDed internal circuit on the die could be damaged during this package process e.g. bond-wiring, if it is correct, what will be the odds then ? If without the on-die ESD at the output, I suppose I will have to be really careful with the soldering and probably add the off-chip ESD to save it.

BTW, I have the output buffer on the chip, do not know if it will also functions somehow as the protection of the critical internal circuit?

And I just guess, for really high freq. or ultra-low-power IC design, ESD become kinda tricky as it introduces some unwanted effects. Has some fellow here survived their chips successfully without (or partly w/o) the ESD protection ?

Thanks so much for your discussions.

 

[WimRFP]

If there is a risk on ESD, and it is for a mass product, I would not take that risk. ESD problems may show months or more later. So you should make sure that your chip and production is compatible.

Can you change the circuit design to take into account parasitics from the ESD protection?

If you can arrange production so that ESD does not occur, you need at least to give design info to the circuit designer. A simple band pass filter can remove lots of ESD energy before the spike enters the chip.

 

[dick_freebird]

If this is a real product, your real customer will have some
demands on pins that are exposed to the outside world.
Antenna connected circuits are one such, if the antenna
is not encased.

You might look at making the ESD clamps' breakover
voltage higher, at mimizing their shunt C (many clamps
have parasitic diodes whose C-V characteristic is bad
news for RF, perhaps a well-tied-off FET clamp is best
or, perhaps, your PA final transistor is big enough to
take the hit (maybe with some attention to current
spreading and hot-spotting).

You might try and get some TLP test data on the pin
or proxy devices and see whether the devices have a
tolerable ruggedness. If so then you can forgo adding
duplicate protection.

 

[powerofthedream]

Dank WimRFP,

Actually this is for the research oriented prototyping fabrication. I dont wanna take the risk either, but the clock it ticking, very close to the tapeout's last minute, not really enough time to figure out a really robust ESD which suits my circuit. So I have to put some ESD off-chip now.

From the previous simulation, the Clamp seems to contribute a lot to the current issue. On the other side, some of the control voltage on the chip could be larger than Vdd, but you know for using ESD, I/O input voltage has to remain between Vdd and Gnd.

So in your opinions, have you experienced a chip working well w/o the ESD. Furthermore do you think the off-chip ESD could at least work somehow to save an output without the ESD on-chip?

If there is a risk on ESD, and it is for a mass product, I would not take that risk. ESD problems may show months or more later. So you should make sure that your chip and production is compatible.

Can you change the circuit design to take into account parasitics from the ESD protection?

If you can arrange production so that ESD does not occur, you need at least to give design info to the circuit designer. A simple band pass filter can remove lots of ESD energy before the spike enters the chip.

- - - Updated - - -

If this is a real product, your real customer will have some
demands on pins that are exposed to the outside world.
Antenna connected circuits are one such, if the antenna
is not encased.

You might look at making the ESD clamps' breakover
voltage higher, at mimizing their shunt C (many clamps
have parasitic diodes whose C-V characteristic is bad
news for RF, perhaps a well-tied-off FET clamp is best
or, perhaps, your PA final transistor is big enough to
take the hit (maybe with some attention to current
spreading and hot-spotting).

You might try and get some TLP test data on the pin
or proxy devices and see whether the devices have a
tolerable ruggedness. If so then you can forgo adding
duplicate protection.

Hi Pals,

Without ESD on-chip, things could become tough, no idea if off-chip ESD on PCB could turn it (ESD issue) around, or at least make the things NOT that bad.

To my unexpected, the Clamp circuitry has brought the most difficulties to me, and currently, there is hardly any time for me to modify it to subtly suit the guts circuits. Therefore my temp. solution is to also remove the "Power Clamp", crossed in the blue, as shown in the diagram below:


To finally become something like the following:



I suppose even the double diodes without the clamp depicted as below, the ESD protection still somehow functions, right? Any drawback could you predict? Thanks for you guys' tips.

 

[dick_freebird]

If the power clamp is causing you problems with RF attributes,
then your power rail is not stiff enough and has substantial
AC activity. I would have expected the rail shunt diodes to
be more the problem since they are directly attached to the
pin - and they are in effect a pair of varactors until onset of
forward conduction.

Removing the power clamp forces the ESD current loop to be
returned through the chip active core, which will certainly not
be designed to handle the current and probably overvoltage
some unfortunate device(s). Only strikes that return naturally
through Gnd or Vdd (not any to any pin) will be routed out
benignly; the protection becomes incomplete.

 

[powerofthedream]

Hi dick and all,

Thanks for your great helps. Just some follow-up question,

In the library, I have seen the ESD_DIODE_STRING which simply series more than one diode, can NOT figure out the meanings of it. On one side, it seems to have doubled the avalanche threshold voltage, right? Say, originally ESD Voltage higher than 10V (ESD avalanche voltage) would be conducted to Gnd, now in the case of string diodes, 20V would be needed to fulfil the conducting requirement.



BTW, I have tried to obtain the exact avalanche voltage. Through simulations, I can not find out the avalanche voltage for ESD diode, (neither in design/model manual) , so does Cadence and PDK really support such sim., do you have any idea about it? Generally the avalanche voltage for an ESD diode should be around ____ V ? Thanks again !!

If the power clamp is causing you problems with RF attributes,
then your power rail is not stiff enough and has substantial
AC activity. I would have expected the rail shunt diodes to
be more the problem since they are directly attached to the
pin - and they are in effect a pair of varactors until onset of
forward conduction.

Removing the power clamp forces the ESD current loop to be
returned through the chip active core, which will certainly not
be designed to handle the current and probably overvoltage
some unfortunate device(s). Only strikes that return naturally
through Gnd or Vdd (not any to any pin) will be routed out
benignly; the protection becomes incomplete.

 

[dick_freebird]

ESD diodes should never avalanche. You cannot depend
on diffuse conduction of current, or fair sharing of voltage.
Diode strings however do increase the forward voltage
and cut down on things like charge pumping from output
to the critical chip ground (RF signals often being ground
referred symmetric, and excursions below ground will go
forward through the diode and end up rectified on signal
pins or pump the ground).

The diode model has the parameters for reverse breakdown
and high/low level reverse saturation currents, but if the
device is not intended / qualified for avalanche operation
these are often unpopulated or defaulted. The norm is
that ESD diodes are forward only and to be used well
below where reverse leakage begins to compromise pin
impedance.

You might inquire of your foundry whether any ESD
design docs or app notes are available, showing the
supported envelope of operation.