bjzhangwn
Member level 1
Data is an inout port,and I want to read the data saved in the Block dura port sram,in case to protect the colision in the data bus,I use a tristate gate to get the data to the data bus,the problem is that the delay is too long,in the synshesis logfile,the delay about the tristate is 4.157ns,but the data I get from the datasheet(Virtex2)is about 2.5ns, after map,in the static timing analyse,the OBUPT delay is 5.42,and the period request is 6.667,the Tbcko is 2.647ns(data stable after the Clock rising edge),the input Clock delay is 1.614ns,so the total delay is out of 6.667ns,What can i do to solve the problem?3x!
