The phase noise for high comparing freq PLL

[saulbit]

Dear everyone:
I made a phse locked loop, with a 20MHz phase dector frequency. But I got confused with the measuring result of phse noise: the 1KHz , 10KHz even the 1MHz
offset is varying between -90~-100dBc/Hz. The frequency band is 2600MHz~3600MHz with 100MHz per step. The bandwidth is about 1MHz (the exact value is beyond my understand).
Also when I tried to reduce the loop bandwidth, the phse noise for 100KHz offset
would be bigger than the 10KHz.
I want to get such a value :-90dBc@1KHz, -100dBc@10KHz, and -120@1MHz.
So dear anyone could help me how to realize it?

 

[vfone]

I think the frequency of your oscillator is drifting.

 

[saulbit]

I think the frequency of your oscillator is drifting.

Would you explain it in more details? My phase locked loops turned in the locking state quite soon.
My VCO is a wideband one for 2600MHz~4000MHz, and the sensitivity is varying from 60MHz~250MHz/volt, which is terrible for me.

 

[fenfei]

If the PFD works near the dead zone ,the phase noise may have fluctuation. you can try to make the loop bandwidth smaller