fena
Newbie level 3
hi to all! I am using Xilinx ise 11.1 and its cores. my first question is: are the outputs of the dds_compiler and fir compiler signed? I couldn't find relative information on them. For fir, my coefficents are signed. does the output type depend on the type of the input?
also, if they are signed, what is the best way to convert them to unsigned (I mean, storing in a std_logic_vector in an unsigned way) by using only those classes:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
a final question, if i store the output of dds_compiler in a std_logic_vector and add it 127 (integer) and then convert it back to std_logic_vector, will it also work for this convertion? (data is 8 bit)
also, if they are signed, what is the best way to convert them to unsigned (I mean, storing in a std_logic_vector in an unsigned way) by using only those classes:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
a final question, if i store the output of dds_compiler in a std_logic_vector and add it 127 (integer) and then convert it back to std_logic_vector, will it also work for this convertion? (data is 8 bit)