The output of DCM inside FPGA leaks to the input?

[tiger_shark]

Signal leakage in DCM?

Hi again,

I have another quesiton for you. I am using Spartan 3-1500 and clock it using an 108 MHz XTAL. the clock goes directly into a DCM and 27,54 are generated. However, when I probe the input clock pin on FPGA, I see spurs of 27 and 54 and 81 in there. Maximum clock speed on the board is 108 MHz.

Does anyone knows whether or not it is possible that the output of DCM inside FPGA reflects back (leaks) to the input and that's what I am seeing?

Thanks in advance,
Regards - TS

 

[vsgiri]

Signal leakage in DCM?

Hi tiger_shark,

The 108MHz crystal that you use is an overtone crytsal - most likely with a fundamental of 27MHz. So this is the third overtone.

In an overtone crystal operation, the fundamental would be attenuated but would not be zero.

My guess is this is the reason for the spurs.
Comments welcome.

Giri

 

[tiger_shark]

Re: Signal leakage in DCM?

Hi,

Thanks for the comnent. It is actually a good hint and thanks for sharing it. However, in my case, I am now clocking the circuit using a fine signal generator which has no spur or harmonic frequency. If FPGA is powered down, no spur or harmony is seen on the clock signal, but when FPGA is working , ugly stuff is observed on the clock...

THanks,
TS

 

[EDALIST]

Re: Signal leakage in DCM?

look like some layout problem, you might need to filter the fpga supply, and put some good bypass capacitors near it, mabee your ground connections are not good, also mabee you have reflections on your clock line beacuse of poor termination.