tiger_shark
Member level 1

Signal leakage in DCM?
Hi again,
I have another quesiton for you. I am using Spartan 3-1500 and clock it using an 108 MHz XTAL. the clock goes directly into a DCM and 27,54 are generated. However, when I probe the input clock pin on FPGA, I see spurs of 27 and 54 and 81 in there. Maximum clock speed on the board is 108 MHz.
Does anyone knows whether or not it is possible that the output of DCM inside FPGA reflects back (leaks) to the input and that's what I am seeing?
Thanks in advance,
Regards - TS
Hi again,
I have another quesiton for you. I am using Spartan 3-1500 and clock it using an 108 MHz XTAL. the clock goes directly into a DCM and 27,54 are generated. However, when I probe the input clock pin on FPGA, I see spurs of 27 and 54 and 81 in there. Maximum clock speed on the board is 108 MHz.
Does anyone knows whether or not it is possible that the output of DCM inside FPGA reflects back (leaks) to the input and that's what I am seeing?
Thanks in advance,
Regards - TS