Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

The NPN Tr in 0.5um CMOS process

Status
Not open for further replies.

chang830

Full Member level 5
Joined
Feb 11, 2006
Messages
267
Helped
14
Reputation
28
Reaction score
3
Trophy points
1,298
Activity points
3,424
Hi,
I am deisgning an block which is PECl output. I found my process provide an NPN Tr and so I intend to use it to implement the PECL level. The NPN Tr is N+/P/NWELL topology. The base is located in the NWELL.

I communicated with the foundr, they said although this device is availble, it is not tested ever, so they can not guarantee if it have any risks. They said the beta of this device is 20 or so.

Would you pls. give any advice in using this device? Any risks ? What about its permance in mass production?

Thanks
 

For a non-buried layer CMOS process I guess that 20 is little high. Typical values for the beta are between 5 and 20. Buried layer, where the inversion impurity between the NWELL and the N+BL reflect the minorities , could give up to 50 as base current gain.

The square emitter is typical P+ surrounded by a gate-poly. Most fabs call the PNP therefore poly PNP, or short PPNP. The field oxide limited N* region defines a FPNP.

You suggested a NPN but with NWELL as base. That does not work! The avaible PPNP is slow and has low maximum current density. So it is used only for special DC application where it is better than the PMOS or a single P+/NWELL diode. Thes application are rare.
 

    chang830

    Points: 2
    Helpful Answer Positive Rating
rfsystem said:
You suggested a NPN but with NWELL as base. That does not work!

Hi rfsystem,
Thanks for the useful reply. It is helpful to me.

But my NPN is N+/P/NWELL . Base is P which is located in the NWELL. The NWELL is not the base. Any other concern on it?

Thanks
 

The performance of the

N+/PWELL/NWELL

NPN depend strong on the base width. So the diffusion difference between the PWELL and N+. I think that this is not accurate controllable to some 100nm. So the dynamic performance of this vertical NPN would be much lower, I guess about 10 in comparison to a poly-emitter/poly-base NPN. If the process does not have a N+BL (buried layer) the current density will be still limited. So also for lower frequency driving purposes there is a limit.

Request a limited model set and then you can judge based on the results. PECL could be very similar made of NMOS. There is no reason to me to use a Med-performing NPN for that.
 

    chang830

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top