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The mystery of JK flip-flop.

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dE_logics

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Hi.

For some reason I've been thrown back to electronics, and I'm stuck at JK flip flops again (To explicitly state, I'm SICK of analyzing 11001000100111 again and again).

I don't understand why any of the resources on the internet don't point to the fact that each and every output of the JK flip-flop depends on the previous outputs, weather J, K is 1, 0; 0 or 1; 0 or 0; or 1, 1. According to my analysis, it depends on both J, K and Q, Q'.

Another obvious question that arises from here is that what's the default value do I assume of Q and Q'?

JK flip-flop appear to be the backbone of everything, so I'm forced to know it.

Also (although I know this's the wrong place to ask), do we have any good circuit analysis software for Linux?
 

thannara123

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Hi.


I don't understand why any of the resources on the internet don't point to the fact that each and every output of the JK flip-flop depends on the previous outputs, weather J, K is 1, 0; 0 or 1; 0 or 0; or 1, 1. According to my analysis, it depends on both J, K and Q, Q'.


i have the same doubt
 

alexan_e

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This is from the first link I have posted:

In most ways, the JK flip-flop behaves just like the RS flip-flop. The Q and Q' outputs will only change state on the falling edge of the CLK signal, and the J and K inputs will control the future output state pretty much as before. However, there are some important differences.

Since one of the two logic inputs is always disabled according to the output state of the overall flip-flop, the master latch cannot change state back and forth while the CLK input is at logic 1. Instead, the enabled input can change the state of the master latch once, after which this latch will not change again. This was not true of the RS flip-flop.

If both the J and K inputs are held at logic 1 and the CLK signal continues to change, the Q and Q' outputs will simply change state with each falling edge of the CLK signal. (The master latch circuit will change state with each rising edge of CLK.) We can use this characteristic to advantage in a number of ways. A flip-flop built specifically to operate this way is typically designated as a T (for Toggle) flip-flop. The lone T input is in fact the CLK input for other types of flip-flops.


J and K control the output and the output state controls which one of the two inputs is disabled so there is clearly a dependence between input and output.

Alex
 

dE_logics

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In most ways, the JK flip-flop behaves just like the RS flip-flop. The Q and Q' outputs will only change state on the falling edge of the CLK

I do not find this correct, assuming Q as 0 and Q' as 1, and assuming this -

jk-flipflop.gif


circuit, if K and J is 0 and 1 I would expect the output to flip... that doesn't happen even with a clock edge.

Here, as compared to a NOR SR flipflop, I assume K is mapped to R and J to S.

Also what's the advantage of JK flipflop as compared to a simple D flipflop? D flipflop also avoids race conditions.
 

alexan_e

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The circuit shown in that website as J-K flip-flop (The JK Flip-Flop) is different from yours
jkf00000.gif



The D flip-flop is described here The D Flip-Flop
it says
"One essential point about the D flip-flop is that when the clock input falls to logic 0 and the outputs can change state, the Q output always takes on the state of the D input at the moment of the clock edge. This was not true of the RS and JK flip-flops. The RS master section would repeatedly change states to match the input signals while the clock line is logic 1, and the Q output would reflect whichever input most recently received an active signal. The JK master section would receive and hold an input to tell it to change state, and never change that state until the next cycle of the clock. This behavior is not possible with a D flip-flop."

Alex
 

dE_logics

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Unfortunately that circuit is something I've seen first time. I have to know the NOR implementation. Also I was referring to the hyperphysics article.
 

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