the multiple number in output inverter buffer

[chang830]

Hi,
I am layout the output buffer whcih drive a ~10pF load cap at 80MHz. The output buffer size is for PMOS 12/0.6,m=40 and for NMOS,it is 12/0.6, m=20. The max size of the W in my process is limited to Wmax=20.

Anyone can see any risk for selction the multiple number is high to 40 for PMOS and 20 for NMOS?

Thanks in adavnce for sharing the experience for the inverter layout.

 

[jfyan]

hi,
why not use some tapped inverters connected in series.

jeff.yan