The meaning of concurrent statement

[sheikh]

Hello Dears
It is simple question for expert members, I want to know that what is the meaning of concurrent statement in vhdl and how does it execute in fpga? For instance consider the below equation:

F= a*X + b*Y+c*Z

well I separate it to these rtls:

T0 : C1 <- a*x, C2 <-b*Y, C3 <-c*Z
T1 : C4 <- C1+C2, C5 <- C4+C3

consider T1, if I execute it sequentially, there is not any speed up in the execution . but it said that VHDL can do it concurrently (in same Time), well if it is right, I cannot understand that how does it possible, because at first C4 must be produce an then the result ( i mean C4) will use to calculation of C5. well i think it means sequential again!!! what is the differences with a software execution ? how does it possible C4 and C5 calculate in same time ( I mean concurrently)?
Regards
Mostafa

 

[barry]

Well, nothing REALLY happens concurrently in the real world. You have to consider the propagation delays of the gates, so you will have glitches/invalid states for the outputs until the inputs are stable, and the gate delays have elapsed. If you draw a diagram of what the actual hardware would look like, you'll be able to better visualize what will happen.

 

[sheikh]

Dear barry
Thanks a lot, but could you please explain more about invalid states. Also consider it that, I used same units ( an adder, for instance, and repeat it two times as like as vhdl coding) can I consider their delay equal or not? and Dose T1 syntax correct ( from hardware view) or not? I mean, it seems that C4 must be produced and then use it for calculating of C5, so I think ( not sure) I can not write these two micro operation in a same box. and the correct rtl is :
T0 : C1 <- a*x, C2 <-b*Y, C3 <-c*Z
T1: C4 <- C1+C2;
T2: C5 <- C4+C3;
Regards
Mostafa

 

[barry]

It is perfectly valid to write your code as shown, but as I said, the output is going to be invalid until all the delays have elapsed. For example, assume you have an adder and a multiplier which have a propagation delay of 50 ns. So when your inputs change, it will take 50 ns for C1 and C2 and C3 to become valid. Then, it will take another 50 ns for C4 to become valid. Finally, it will take another 50ns for C5 to become valid. So, you will have to wait a minimum of 150nS from when your input changes to when your output is valid.

Or you could use a synchronous(clocked) design and not have to worry about all this.

 

[sheikh]

Thanks a lot Dear barry for your comments and recommendation

 

[TrickyDicky]

You must remember that VHDL stands for VHSIC Hardware Description Language. it is NOT a programming language. So certain things occur in VHDL in zero time, because thats the hardware that would be described.

Forget your programming ideas, think in terms of hardware. Without understanding digital logic, there is no way you can understand HDL.

 

[sheikh]

Thanks Dear TrickyDicky
you are RIGHT, i'll consider that, and it is a great recommendation
"Forget your programming ideas, think in terms of hardware. Without understanding digital logic, there is no way you can understand HDL."

 

[FvM]

In addition, when you are describing VHDL constructs as in post #1 and #3, I would really prefer to see legal VHDL syntax rather than phantasy language like this

T0 : C1 <- a*x, C2 <-b*Y, C3 <-c*Z

Although barry could apparently read something into the "code", I still wonder which VHDL operations are exactly meaned.

 

[sheikh]

Dear FvM
Thanks for your comment and advise I just put some rtl transitions here, and please consider it as a state box in an ASM chart. I was interested in the meaning of concurrency execution, versus the sequential execution ( that used by matlab, for instance).

 

[FvM]

O.K., but to discuss in detail how these constructs are implemented in VHDL and translated to FPGA hardware, we should look at the VHDL code.

 

[sheikh]

Of course you are right Dear FvM and I'll consider that and will try to prepare better explanation for my questions in future posts.

 

[Robin Khosla]

Hello Dears
It is simple question for expert members, I want to know that what is the meaning of concurrent statement in vhdl and how does it execute in fpga? For instance consider the below equation:

F= a*X + b*Y+c*Z

well I separate it to these rtls:

T0 : C1 <- a*x, C2 <-b*Y, C3 <-c*Z
T1 : C4 <- C1+C2, C5 <- C4+C3

consider T1, if I execute it sequentially, there is not any speed up in the execution . but it said that VHDL can do it concurrently (in same Time), well if it is right, I cannot understand that how does it possible, because at first C4 must be produce an then the result ( i mean C4) will use to calculation of C5. well i think it means sequential again!!! what is the differences with a software execution ? how does it possible C4 and C5 calculate in same time ( I mean concurrently)?
Regards
Mostafa

you need to clearly understand the difference b/w concurrent and sequential statements...
sequential statement is executed in sequence i.e. one after the another
but concurrent statements are executed simultaneously i.e. at the same time. however there are different propagation delays for different gates.
in your case both c4,c5 are executed at the same time..
please refer to " VHDL PRIMER by J.BHASKER "
and also read the concept of delays..........

 

[sheikh]

Thanks Robin