the inout port in Verilog

[wjxcom]

inout port in verilog

Hi, all: how to use inout port in Verilog? I write like this:

assign data=en_in?inout_port:4'bzzzz;
assign inout_port=en_out_one?data_reg_one:4'bzzzz;
assign inout_port=(en_out_two && !en_out_one)?data_reg_two:4'bzzzz;

where data, data_reg_one, data_reg_two is internal register in CPLD ,inout_port is input and output type, en_out_one and en_out_two is enable signal.

I do not know is this two sentence mentioned above is right, because QuartusII's warning is: data conflict.

 

[tarkyss]

data is reg signal?
how can you assign data=en_in?inout_port:4'bzzzz;
for inout signal
normally, you need define another inter signal.

 

[wadaye]

Hi wjxcom,

You'd bettern instantiate the bidirection io in your rtl code, don't let tool implement it.

 

[wjxcom]

Hi, tarkyss: would you explain this problem more detailed?