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Transfer of multi bit across asynchronous clock domain may be susceptible to data incoherency, if those bits changes close to the clock edge of the capturing clock domain. The classical two stage flip flop synchronizer will not solve the problem of data incoherency.
For example, if 'b0000 - > 'b0110 is transferred from clock domain A to clock domain B ( they are asynchronous), and the bit transition happen to occur close to the clock edge, the output of capturing flops may go metastable. The metastability will cause the bit to be in any one of 'b0000, 'b0100, 'b0010 and 'b0110 states. Here, the data send by clock domain A is incoherent with data capture by clock domain B, even if they are synchronized through two state flip flop synchronizer. Now, what happens if you change only one bit only('b0000 -> 'b0010) while sending mult bit across clock domain, the capture value will be either old value 'b0000 or new value 'b0010. There are no other possible incorrect values like in multi_bit changes. Here, using single bit change( which is what gray coding is) solves the issue of data incoherency in asynchronous fifo.