Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

The explanation of false paths

Status
Not open for further replies.

kameswari

Newbie level 2
Joined
Jan 14, 2004
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
20
false path

Hi,

can anyone pls explain in detail about false paths?

regards,
kams
 

gerryhsu

Full Member level 3
Joined
Oct 20, 2003
Messages
171
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,296
Activity points
1,183
Re: false path

In Static Timing Analyzer. the analyzer determines delay, it considers only the paths that actually affect the output. If a path is never activated, or sensitized, it cannot possibly contribute to delay. This path is called false path.
 

efundas

Member level 3
Joined
Jul 28, 2001
Messages
62
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
387
What about the async paths(eg, path from one clk domain to another async clk domain). don't we consider them also as false paths in synthesis.
 

hayang

Newbie level 6
Joined
Dec 17, 2003
Messages
11
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
70
Re: false path

In Synopsys Design compiler, a false path is a path for which you will ignore timing constraints. for example, when crossing different asynchronous clock domains. Under this situation, you will have to disable the timing-based synthesis on this path.
 

roli

Full Member level 5
Joined
Apr 29, 2001
Messages
246
Helped
9
Reputation
20
Reaction score
9
Trophy points
1,298
Location
'SiliconWafer' Island
Activity points
1,817
Re: false path

Another example of a 'false path' would be a Multiple Clock Phase path, where only the designer "knows" it is a Multiple Clock path, but Synopsys DC-Compiler /PrimeTime do not. In these cases, where a relief of Time Constraint can be added, a Pre Knowledge of Design may be used to add a False Path.
 

tom123

Advanced Member level 4
Joined
Apr 4, 2005
Messages
116
Helped
5
Reputation
10
Reaction score
2
Trophy points
1,298
Activity points
2,338
Re: false path

The false path is those path that their timing is don't care,

for example, a signal passing through asynchronous boundary.


best regards






kameswari said:
Hi,

can anyone pls explain in detail about false paths?

regards,
kams
 

nittinsharma80

Member level 5
Joined
Apr 11, 2005
Messages
93
Helped
11
Reputation
22
Reaction score
2
Trophy points
1,288
Location
INDIA
Activity points
2,337
Re: false path

Hi,
Go through the attachment. it explains the false path in detail.
regards,
--Nitn S.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top