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In Static Timing Analyzer. the analyzer determines delay, it considers only the paths that actually affect the output. If a path is never activated, or sensitized, it cannot possibly contribute to delay. This path is called false path.
In Synopsys Design compiler, a false path is a path for which you will ignore timing constraints. for example, when crossing different asynchronous clock domains. Under this situation, you will have to disable the timing-based synthesis on this path.
Another example of a 'false path' would be a Multiple Clock Phase path, where only the designer "knows" it is a Multiple Clock path, but Synopsys DC-Compiler /PrimeTime do not. In these cases, where a relief of Time Constraint can be added, a Pre Knowledge of Design may be used to add a False Path.