The difficulty of selecting nMOS size on ESD

[haemun]

Hello,

I have an question about the ESD.
The picture I've attached is an ESD protection circuit for digital output.
I've used this pad but I wanna change the circled nMOS size of output inverter at this time because I need to drive more current than before.

The problem I've encountered is this: increasing W or decreasing L.
Which method is the best?
Decresing the size of L is an easy answer but I'm worrying that it may be damaged by ESD.

I think, of course, there's no matter whether I changed it or not if the esd protection circuit on the pad is properly designed.
But I'm still concerned about it.

Please share your experience and opinion.

Thanks!

 

[willyboy19]

Increasing W is safer for ESD event.

 

[firegun]

I think you can decrease the L,while you should add a little resistor between the Output Buffer and ESD devices.

 

[haemun]

Thanks for your replys.

 

[Fom]

Look at the layout first.
Usually output transistors and ESD transistors integrated in one large transistor that fingered by 40-50u with and surrounded by guard ring to prevent latch-up.
So when designer need to increase output driving capability he should cut some fingers from ESD part and connect them to output part. The total transistor size and S/D area are not changed.

 

[pswatw]

Look at the layout first.
Usually output transistors and ESD transistors integrated in one large transistor that fingered by 40-50u with and surrounded by guard ring to prevent latch-up.
So when designer need to increase output driving capability he should cut some fingers from ESD part and connect them to output part. The total transistor size and S/D area are not changed.



Can you tell me why we can cut some fingers from ESD part and connect them to output part. Can it make the ESD failed??

Thanks!!