The difference between VHDL and Verilog.

[thuyet]

Hi every body.
As i know,in hardware language description ,there are VHDL and Verilog.I learned and worded my thesis using VHDL with Spartan2e.I don't understand much about the different between them.Why both vhdl and verilog are used .So someone please help me to clear about it. I want to research in ic design.So please show me
Thank a lot

 

[newcpu]

or_reduce vhdl

The functions of them are almost the same. Verilog is more popular in USA while VHDL is more popular in Europe.

 

[rakesh_aadhimoolam]

or_reduce

Hi...............well

VHDL is little Process specific in the sense everything you give in a systematic means............

Verilog on the otherside is an ease to understand language if you are good at software programming languages..........

you can get the other differences in a book called HDL Chip Design by Douglas Smith

good luck...................

 

[thuyet]

advantages of vhdl over verilog

hi
would you please show me how to get that book?
or url that i can download it.
thanx

 

[subramanyam]

advatage of vhdl

Here is a good document which compares VHDL and VERILOG. Hope is useful.

subbu.

 

[Guru59]

advantage of verilog over vhdl

The Document given by Subbu is from the Book described by Rakesh.........

good luck............

and abt the book you will get in upload/download section of this forum............

Now you do not have enough points or level.............once you reach Member Level or get enough points you will be able to see the sub-forum upload/download section

 

[omara007]

verilog and_reduce

Verilog has some advantages over VHDL, like the reduction operators .. they are quite useful in design, but unfortunatly they are absent in VHDL

 

[darylz]

verilog advantage

reduction operator cannot aprove verilog's advantage vs. VHDL.

 

[omara007]

advantage of verilog

reduction operator cannot aprove verilog's advantage vs. VHDL.

It's indeed a facility in verilog that is completely absent in VHDL

 

[aji_vlsi]

vhdl reduce_pack

reduction operator cannot aprove verilog's advantage vs. VHDL.

It's indeed a facility in verilog that is completely absent in VHDL

Have you tried OR_REDUCE, AND_REDUCE functions? See:
**broken link removed**

Ajeetha, CVC
www.noveldv.com

 

[omara007]

advantages of verilog or vhdl

reduction operator cannot aprove verilog's advantage vs. VHDL.

It's indeed a facility in verilog that is completely absent in VHDL

Have you tried OR_REDUCE, AND_REDUCE functions? See:
h**p://vhdl.org/vhdlsynth/vhdl/reduce_pack.vhd

Ajeetha, CVC
www.noveldv.com

Are they in numeric_std ?

 

[bharat_in]

the advantage of vhdl over verilog

When it comes to signed and unsigned data types , VHDL is better than verilog..

 

[omara007]

operators in vhdl + or_reduce

reduction operator cannot aprove verilog's advantage vs. VHDL.

It's indeed a facility in verilog that is completely absent in VHDL

Have you tried OR_REDUCE, AND_REDUCE functions? See:
h**p://vhdl.org/vhdlsynth/vhdl/reduce_pack.vhd

Ajeetha, CVC
www.noveldv.com

Are they synthesizable ???? .. it looks to me that they were proposed in 2002 and still not approved till today !!

 

[hurricanebomb]

advantage of vhdl

vhdl is more abstraction.
verilog is closer to the real netlist

 

[synpscrk]

vhdl reduction and

vhdl mostly for fpga
verilog mostly for asic

 

[omara007]

vhdl and_reduce

vhdl mostly for fpga
verilog mostly for asic

what is that !!!! ... this is completely wrong .. there is nothing such as what u said .. both VHDL and Verilog are equally for ASIC and FPGA ..

 

[sadid]

dubai verilog

some experts say verilog is not good in high integrated circuit on this level VHDL is completely better but on other field may be verilog is better it has a advanced and faster compiler

 

[thuyet]

advantages of verilog

So.In IC design technology.which language is used?

 

[anoop12]

and_reduce vhdl 2006

Major difference is that Verilog supports CMOS gate designing while VHDL not.
But still both are best in their respetive application areas.