darylz said:reduction operator cannot aprove verilog's advantage vs. VHDL.
omara007 said:darylz said:reduction operator cannot aprove verilog's advantage vs. VHDL.
It's indeed a facility in verilog that is completely absent in VHDL
aji_vlsi said:omara007 said:darylz said:reduction operator cannot aprove verilog's advantage vs. VHDL.
It's indeed a facility in verilog that is completely absent in VHDL
Have you tried OR_REDUCE, AND_REDUCE functions? See:
h**p://vhdl.org/vhdlsynth/vhdl/reduce_pack.vhd
Ajeetha, CVC
www.noveldv.com
aji_vlsi said:omara007 said:darylz said:reduction operator cannot aprove verilog's advantage vs. VHDL.
It's indeed a facility in verilog that is completely absent in VHDL
Have you tried OR_REDUCE, AND_REDUCE functions? See:
h**p://vhdl.org/vhdlsynth/vhdl/reduce_pack.vhd
Ajeetha, CVC
www.noveldv.com
synpscrk said:vhdl mostly for fpga
verilog mostly for asic
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