Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

The design of low speed high resolution DAC

Status
Not open for further replies.

Question

Member level 5
Joined
Aug 11, 2004
Messages
89
Helped
5
Reputation
10
Reaction score
4
Trophy points
1,288
Activity points
758
low speed dac

I have a project of 20kHz 12(or 14)Bit DAC. Do i need to use R-2R architecture to design it? And who can give me some advice or papers of this kind of DAC design.

Thanks a lot!!
 

how to meet the mathing requirment without trmming?
 

Generally speaking, 12 to 14 Bit is feasible without trimming as long as the chip area and power is not an issue. The key point here is the matching of your resistors in the R-2R network. There is a 14 Bit DAC using current steering technique published.
 

My suggestion is to use sigma-delta DAC architecture to avoid any of the trimming and mismatch error issues.
 

As far as matching is concerned,
C-2C (MiM capacitors) ladder is much better than R-2R
by order of 10 in my experience.

Suggest consider charge re-distribution DAC,
should be able to come close.
 

I have found more than two chips useing R-2R ladders architecture that can meet 14-16bit. There are AD5541 and AD5551 by Analog Devices. My design is just like these two chip.
 

i had designed a sigma-delta ADC,if your DAC use sigma-delta?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top