Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
Decoupling capacitors should be placed first of all near the IC pins. If the DC source is a cable (from external power supply) or voltage regulator, additional decoupling capacitor should be placed where the cable enters the PCB (to filter noise at the input) or near the voltage regulator output (to decrease the noise that voltage regulator cannot actively supress (high-frequency noise)). Please see the folowing link:
**broken link removed**
for additional information.
Best Regards,
F.S.
Hi,
I think that for precise simulation the 3D EM solver is needed, since decoupling effectiveness is very dependent on the power/ground layout even for the same type of the capacitors used. This is suitable only for small designs. For big designs it is possible to use Cadence power integrity analysis available with Specctraquest (I think form PSD15.0).
Anyway, precise component models should be used, including all of the parasitic parameters of the chosen decoupling components.
Regards,
F.S.
Decoupling caps are placed near the dut pins and IC's for reducing noises.Capacitors are used in descending sizes.Small value caps are great for stopping high frequency noise.Very large caps are used more like mini batteries.If something need more power, the large caps provide it,then slowly recharges.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.