Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

the decouple capacitor placement?

Status
Not open for further replies.

mckinson

Full Member level 2
Joined
Sep 3, 2003
Messages
126
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,298
Activity points
1,034
decouple capacitor

When we place the DC source's decouple capacitor ,next to the DC source or pin of IC? thanks
 

falling_stone

Member level 1
Joined
Jul 19, 2002
Messages
40
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
503
Hi,
Decoupling capacitors should be placed first of all near the IC pins. If the DC source is a cable (from external power supply) or voltage regulator, additional decoupling capacitor should be placed where the cable enters the PCB (to filter noise at the input) or near the voltage regulator output (to decrease the noise that voltage regulator cannot actively supress (high-frequency noise)). Please see the folowing link:
https://www.elektroda.pl/eboard/viewtopic.php?t=49315&highlight=
for additional information.
Best Regards,
F.S.
 

mckinson

Full Member level 2
Joined
Sep 3, 2003
Messages
126
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,298
Activity points
1,034
falling_stone,thanks for yout reply!!
 

MentorSI

Newbie level 2
Joined
Sep 11, 2003
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
61
I want to know how to simulate the result of the decoupled capacitor.
Thank you !
 

falling_stone

Member level 1
Joined
Jul 19, 2002
Messages
40
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
503
Hi,
I think that for precise simulation the 3D EM solver is needed, since decoupling effectiveness is very dependent on the power/ground layout even for the same type of the capacitors used. This is suitable only for small designs. For big designs it is possible to use Cadence power integrity analysis available with Specctraquest (I think form PSD15.0).
Anyway, precise component models should be used, including all of the parasitic parameters of the chosen decoupling components.
Regards,
F.S.
 

amjad

Full Member level 5
Joined
Dec 29, 2002
Messages
274
Helped
9
Reputation
18
Reaction score
5
Trophy points
1,298
Activity points
2,291
Decoupling caps are placed near the dut pins and IC's for reducing noises.Capacitors are used in descending sizes.Small value caps are great for stopping high frequency noise.Very large caps are used more like mini batteries.If something need more power, the large caps provide it,then slowly recharges.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top