The changing of digital control signal affecting the analog signal

[melkord]

I have an array of, let's say, CSA-Comparator pair and a digital block to control this array.
As can be seen from the picture below, the changing of digital control signal affecting the analog signal, i.e., its baseline and amplitude.
This results to a pulse width variation on the comparator output.

The digital part has its own supply in this simulation.

How can I mitigate this?

 

[jjx]

What does the digital control signal affect in your circuit?

 

[Dominik Przyborowski]

You are injecting charge somewhere in the circuit. Is it schematic or post layout simulations? If you have capacitance coupling between digital line and high impedance node then you can see such thing.

Or maybe what you see is a kickback from comparator?