The Arria II GX FPGA development Kit failed to configure FPGA at power up and JTAG

[sngoedaboard]

Hi,

I've been using the Arria II GX FPGA development board for over 6 month without any problem but encountered a problem yesterday. When I power up the board, the Load LED illuminates, but shortly it goes out. Then the Error red LED illuminates. When I try to do the auto-detect in the programmer, the FPGA is shown as UNKNOWN device in both methods of using embedded USB blaster and external USB Blaster cable. I also tried both with and without the MAX II CPLD EPM2210 System Controller in the JTAG chain and got the same problem.

I tried to add file .sof to program the FPGA anyway but got the following error msg:

Info (209060): Started Programmer operation at Tue Jan 21 17:22:44 2014
Error (209015): Can't configure device. Expected JTAG ID code 0x025040DD for device 1, but found JTAG ID code 0x025FC0DD.
Error (209012): Operation failed
Info (209061): Ended Programmer operation at Tue Jan 21 17:22:44 2014

I am in the middle of testing my design and desperately need help to find solutions for this problem !!! We paid over USD$3000 for this kit but could not find way to get support from Altera.

Many many thanks,

Scott

 

[aruipksni]

Hi,

I've been using the Arria II GX FPGA development board for over 6 month without any problem but encountered a problem yesterday. When I power up the board, the Load LED illuminates, but shortly it goes out. Then the Error red LED illuminates. When I try to do the auto-detect in the programmer, the FPGA is shown as UNKNOWN device in both methods of using embedded USB blaster and external USB Blaster cable. I also tried both with and without the MAX II CPLD EPM2210 System Controller in the JTAG chain and got the same problem.

I tried to add file .sof to program the FPGA anyway but got the following error msg:

Info (209060): Started Programmer operation at Tue Jan 21 17:22:44 2014
Error (209015): Can't configure device. Expected JTAG ID code 0x025040DD for device 1, but found JTAG ID code 0x025FC0DD.
Error (209012): Operation failed
Info (209061): Ended Programmer operation at Tue Jan 21 17:22:44 2014

I am in the middle of testing my design and desperately need help to find solutions for this problem !!! We paid over USD$3000 for this kit but could not find way to get support from Altera.

Many many thanks,

Scott

can it be connected to the anty temparing problem ?

 

[sngoedaboard]

can it be connected to the anty temparing problem ?

I don't understand what you mean as you said "connected to the anty temparing problem"? Can you elaborate ?
Thanks,
Scott

 

[aruipksni]

I don't understand what you mean as you said "connected to the anty temparing problem"? Can you elaborate ?
Thanks,
Scott

there is a chance that somehow your fpga become non-volatile by setting the security bit .

 

[sngoedaboard]

there is a chance that somehow your fpga become non-volatile by setting the security bit .

Is there a way to reset the security bit to the correct one ?

 

[aruipksni]

first check that the bit actually been written with KEY_VERIFY command. see https://www.altera.com/literature/an/an556.pdf
if it's written you need to replace your FPGA device.

 

[sngoedaboard]

first check that the bit actually been written with KEY_VERIFY command. see https://www.altera.com/literature/an/an556.pdf
if it's written you need to replace your FPGA device.

Thank you so much for very interesting FPGA feature and valuable knowledge that you kindly posted to help me. I'll thoroughly study them. But first please show me quick way to check the bit's actually been written with KEY_VERIFY command.

 

[aruipksni]

Thank you so much for very interesting FPGA feature and valuable knowledge that you kindly posted to help me. I'll thoroughly study them. But first please show me quick way to check the bit's actually been written with KEY_VERIFY command.

you can use the quartus_jli command line tool. for more info check :

**broken link removed**

 

[std_match]

I don't think it is a security bit problem. That should have other effects than corrupting the JTAG id.

Check the MSEL pins configuration on your board. If they are configured by switches, maybe there is a bad connection there.

 

[sngoedaboard]

I don't think it is a security bit problem. That should have other effects than corrupting the JTAG id.

Check the MSEL pins configuration on your board. If they are configured by switches, maybe there is a bad connection there.

Hi,
First, I do appreciate your help. The MSEL[3:0] pins are grounded, which indicated that the board's configuration mode is FPP using MAX II device

 

[sngoedaboard]

Hi,
First, I do appreciate your help. The MSEL[3:0] pins are grounded, which indicated that the board's configuration mode is FPP using MAX II device

I still need more help with this problem. Please, any one ?

Scott

 

[aruipksni]

I still need more help with this problem. Please, any one ?

Scott

try to program cpld or / and cfi flash again ....

 

[sngoedaboard]

try to program cpld or / and cfi flash again ....

Thank you again. But as matter of fact, I've done reprogramming the CPLD MAX II at the beginning of this problem and then I even went to the Altera web site to download the latest CPLD MAX II firmware for this particular development kit. Again, the problem did not go away and was still the same.

 

[aruipksni]

Thank you again. But as matter of fact, I've done reprogramming the CPLD MAX II at the beginning of this problem and then I even went to the Altera web site to download the latest CPLD MAX II firmware for this particular development kit. Again, the problem did not go away and was still the same.

didyou try to look with scope