tetramax path delay test

[samankiamehr]

I have the following code for path delay test generation:

read_netlist s27_synthsized_scan_test.v
read_netlist ../../Library/saed90nm.v -library
run_build_model s27
set_delay -nopi_changes
set_delay -nopo_measures
set_delay -mask_nontarget_paths
set_delay -common_launch_capture_clock
set_delay -relative_edge
add_clocks 0 CK
add_pi_constraints 0 CK
run_drc s27.spf
add_delay_paths s27_pt_report.import
set_faults -model path_delay
add_faults -all
run_atpg
set_atpg -full_seq_merge medium
set_atpg -fill x
#report_patterns -all -path_delay
#report_patterns -all -slack
#run_atpg full_sequential_only
report_delay_paths -all
write_patterns s27.wgl -replace -format wgl


but it reports the following warning :


Unconstrained primary input test_se used as SCAN ENABLE may change during at-speed cycles. (M487)

***********************************************************
* NOTICE: The following DRC violations were previously *
* encountered. The presence of these violations is an *
* indicator that it is possible that the ATPG patterns *
* created during this process may fail in simulation. *
* *
* Rules: N20 *



and " End writing file 's27.wgl' with 0 patterns, File_size = 4651, CPU_time = 0.0 sec."

which means no patterns is written. Can anyone help me with this. I appreciate any comments you may have about the problem.

 

[maulin sheth]

Hello,
You just need to add the folloing constraint:
add_pi_constraints 1 test_se