Testbench & simulation errors

[hastidot]

Hi there
I'm generating a testbench code for my Top module to access the simulation results. but the following errors disappears and I dont't know what is the solution :-(

ERROR:HDLCompiler:718, Port connections cannot be mixed ordered and named


my top module is as follows:

`timescale 1ns / 1ps





module imp_top(
// Global IO
SysClk,
SysReset,
// IODR2 Interface
ddr2_dq,
ddr2_a,
ddr2_ba,
ddr2_ras_n,
ddr2_cas_n,
ddr2_we_n,
ddr2_cs_n,
ddr2_odt,
ddr2_cke,
ddr2_dm,

phy_init_done,

ddr2_dqs,
ddr2_dqs_n,
ddr2_ck,
ddr2_ck_n,
locked3,

);

Global IO
input SysClk;
input SysReset;
// IODR2 Interface
inout [`DQ_WIDTH-1:0] ddr2_dq;
output [`ROW_WIDTH-1:0] ddr2_a;
output [`BANK_WIDTH-1:0] ddr2_ba;
output ddr2_ras_n;
output ddr2_cas_n;
output ddr2_we_n;
output [`CS_WIDTH-1:0] ddr2_cs_n;
output [`ODT_WIDTH-1:0] ddr2_odt;
output [`CKE_WIDTH-1:0] ddr2_cke;
output [`DM_WIDTH-1:0] ddr2_dm;

output phy_init_done;

inout [`DQS_WIDTH-1:0] ddr2_dqs;
inout [`DQS_WIDTH-1:0] ddr2_dqs_n;
output [`CLK_WIDTH-1:0] ddr2_ck;
output [`CLK_WIDTH-1:0] ddr2_ck_n;

output locked3;


wire sys_clk;
wire sys_clk_n;
wire sys_clk_p;
wire sys_clk200;
wire clk200_n;
wire clk200_p;
wire sys_rst_n; // The input to the infrastructure_top
assign sys_rst_n = SysReset;
wire sys_rst_out;
wire [`DQ_WIDTH-1:0] ddr2_dq;
wire [`DQS_WIDTH-1:0] ddr2_dqs;
wire [`DQS_WIDTH-1:0] ddr2_dqs_n;
wire [`DM_WIDTH-1:0] ddr2_dm;
wire [`CLK_WIDTH-1:0] ddr2_clk;
wire [`CLK_WIDTH-1:0] ddr2_clk_n;
wire [`ROW_WIDTH-1:0] ddr2_addess;
wire [`BANK_WIDTH-1:0] ddr2_ba;
wire ddr2_ras_n;
wire ddr2_cas_n;
wire ddr2_we_n;
wire [`CS_WIDTH-1:0] ddr2_cs_n;
wire [`CKE_WIDTH-1:0] ddr2_cke;
wire [`ODT_WIDTH-1:0] ddr2_odt;
wire error;
wire phy_init_done;
wire rst0;

// Only RDIMM memory parts support the reset signal,
// hence the ddr2_reset_n signal can be ignored for other memory parts
wire ddr2_reset_n;
reg [`ROW_WIDTH-1:0] ddr2_address_reg;
reg [`BANK_WIDTH-1:0] ddr2_ba_reg;
reg [`CKE_WIDTH-1:0] ddr2_cke_reg;
reg ddr2_ras_n_reg;
reg ddr2_cas_n_reg;
reg ddr2_we_n_reg;
reg [`CS_WIDTH-1:0] ddr2_cs_n_reg;
reg [`ODT_WIDTH-1:0] ddr2_odt_reg;
wire sys_clk_ibufg;
wire clk200_ibufg;
wire clk0; // Output of Infrastructure, input to the main PG135 userguide
wire clk90;
wire clk200;
wire clkdiv0;
wire clk0_bufg;
wire clk0_bufg_in;
wire clk90_bufg;
wire clk90_bufg_in;
wire clk200_bufg;
wire clkdiv0_bufg;
wire clkdiv0_bufg_in;
wire clkfbout_clkfbin;
wire locked;
wire locked2;
wire SysClk_bufg;
wire SysResettest;

assign sys_clk_p = sys_clk;
assign sys_clk_n = ~sys_clk;
assign clk200_p = sys_clk200;
assign clk200_n = ~sys_clk200;


assign sys_rst_out = RST_ACT_LOW ? sys_rst_n : ~sys_rst_n;
assign clk0 = clk0_bufg;
assign clk90 = clk90_bufg;
assign clk200 = clk200_bufg;
assign clkdiv0 = clkdiv0_bufg;

mig_32 #
(
.BANK_WIDTH (BANK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.CLK_WIDTH (CLK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_NUM (CS_NUM),
.CS_WIDTH (CS_WIDTH),
.CS_BITS (CS_BITS),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQ_PER_DQS (DQ_PER_DQS),
.DQ_BITS (DQ_BITS),
.DQS_WIDTH (DQS_WIDTH),
.DQS_BITS (DQS_BITS),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.APPDATA_WIDTH (APPDATA_WIDTH),
.ADDITIVE_LAT (ADDITIVE_LAT),
.BURST_LEN (BURST_LEN),
.BURST_TYPE (BURST_TYPE),
.CAS_LAT (CAS_LAT),
.ECC_ENABLE (ECC_ENABLE),
.MULTI_BANK_EN (MULTI_BANK_EN),
.ODT_TYPE (ODT_TYPE),
.REDUCE_DRV (REDUCE_DRV),
.REG_ENABLE (REG_ENABLE),
.TREFI_NS (TREFI_NS),
.TRAS (TRAS),
.TRCD (TRCD),
.TRFC (TRFC),
.TRP (TRP),
.TRTP (TRTP),
.TWR (TWR),
.TWTR (TWTR),
.SIM_ONLY (SIM_ONLY),
.RST_ACT_LOW (RST_ACT_LOW),
.CLK_PERIOD (CLK_PERIOD)
)
u_mem_controller
(
.clk0 (clk0),
.clk90 (clk90),
.clk200 (clk200),
.clkdiv0 (clkdiv0),
.locked (locked3),
.sys_rst_n (sys_rst_out),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_cke (ddr2_cke),
.ddr2_odt (ddr2_odt),
.ddr2_dm (ddr2_dm),
.ddr2_dq (ddr2_dq),
.ddr2_dqs (ddr2_dqs),
.ddr2_dqs_n (ddr2_dqs_n),
.ddr2_ck (ddr2_ck),
.ddr2_ck_n (ddr2_ck_n),
.ddr2_ba (ddr2_ba),
.ddr2_a (ddr2_a),
//.error (error),
.app_wdf_afull (app_wdf_afull),
.app_af_addr (app_af_addr),
.app_af_afull (app_af_afull),
.app_wdf_wren (app_wdf_wren),
.app_af_cmd (app_af_cmd),
//sys_rst_n (sys_rst_n),
.phy_init_done (phy_init_done)
);

assign SysResettest=0;

dcm_7 dcm_7 (
.CLKIN_IN(SysClk),
.RST_IN(SysResettest),
.CLKDV_OUT(clkdiv0_bufg_in),
.CLKFX_OUT(clk200_ibufg),
.CLKIN_IBUFG_OUT(sys_clk),
.CLK0_OUT(clk0_bufg_in),
.CLK90_OUT(clk90_bufg_in),
.LOCKED_OUT(locked3)
);



BUFG u_bufg_clk0
(
.O (clk0_bufg),
.I (clk0_bufg_in)
);

BUFG u_bufg_clk90
(
.O (clk90_bufg),
.I (clk90_bufg_in)
);



BUFG u_bufg_clkdiv0
(
.O (clkdiv0_bufg),
.I (clkdiv0_bufg_in)
);

BUFG u_bufg_clk200
(
.O (clk200_bufg),
.I (clk200_ibufg)
);

ddr2_tb_top ddr_tb_top (
.clk0(clk0),
.rst0(SysReset),
.app_af_afull(app_af_afull),
.app_wdf_afull(app_wdf_afull),
.rd_data_valid(rd_data_valid),
.rd_data_fifo_out(rd_data_fifo_out),
.phy_init_done(phy_init_done),
.app_af_wren(app_af_wren),
.app_af_cmd(app_af_cmd),
.app_af_addr(app_af_addr),
.app_wdf_wren(app_wdf_wren),
.app_wdf_data(app_wdf_data),
.app_wdf_mask_data(app_wdf_mask_data),
.error(error),
.error_cmp(error_cmp)
);

endmodule


Thanks in advance

 

[FvM]

Most likely a trivial syntax error. HDL compilers are giving locations along with error messages. It's a kind of unreasonable demand to post the code without marking the indicated error location.

 

[mrflibble]

That line "Global IO" doesn't look right.

Not that I would think that it would cause this type of error. This type of error is usually given when you do:



example_module _name example_instantiation (
.clk(clk), // named
something_else // ordered
);

Could you put it in "code" tags next time for better readability? Also, a full error message complete with line numbers indeed would be nice. Because ... what FvM said.