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testbench problems- error declare input matrix

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fanwel

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Dear all,

I try to write a testbench code for my transpose.vhd file, where i want to have a matrix transpose. Below is my main code and testbench code:

1) Main code:
---------package---------
package my_data_types is
--type column is array (-127 downto 127) of integer;
--type row is array (-127 downto 127) of integer;
type matrix is array (natural range<>, natural range<>) of integer;
end package my_data_types;

----------main code-------
use work.my_data_types.all;

entity transpose is
generic (m: integer :=3;
n: integer :=3);
port (x: in matrix (0 to M-1, N-1 downto 0);
y: out matrix (0 to M-1, N-1 downto 0);
clk: in bit);
end transpose;

architecture transpose of transpose is
begin
process(clk)
begin
if (clk'event and clk='1') then
for i in 0 to m-1 loop
for j in 0 to m-1 loop
y(i,j) <= x(j,i);
end loop;
end loop;
end if;
end process;
end transpose;

2)Testbench code:

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity transpose_tb is
end;

architecture bench of transpose_tb is

component transpose
generic (m: integer :=3;
n: integer :=3);
port (x: in matrix (0 to M-1, N-1 downto 0);
y: out matrix (0 to M-1, N-1 downto 0);
clk: in bit);
end component;

signal x: matrix (0 to M-1, N-1 downto 0);
signal y: matrix (0 to M-1, N-1 downto 0);
signal clk: bit;

constant clock_period: time := 10 ns;
signal stop_the_clock: boolean;

begin

uut: transpose generic map ( m => 3,
n => 3 )
port map ( x => x,
y => y,
clk => clk );

stimulus: process
begin
x <= (12,23,30,18),(2,3,1,5);
wait for 150ns;

stop_the_clock <= true;
wait;
end process;

clocking: process
begin
while not stop_the_clock loop
clk <= '1', '0' after clock_period / 2;
wait for clock_period;
end loop;
wait;
end process;

end;

There is no error when I compile the main code, but an error occured when I compile the testbench code;

Error (10486): VHDL error at transpose_tb.vhd(13): slice of object cannot be specified for object that has an array type of more than one dimension.

I try to debug this error many times but this error still occured. I need helps from you all to tell me where Iam wrong..Many thanks.
 

try adding this line to the testbench code..

use work.my_data_types.all;
 
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    fanwel

    Points: 2
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Dear vipinlal,

I have write the line you give and its okay. But know I have this error;

Error (10482): VHDL error at transpose_tb.vhd(19): object "M" is used but not declared.
Error (10482): VHDL error at transpose_tb.vhd(19): object "N" is used but not declared.

Although I already declare it as an integer. It is i need to declare in the signal part?
Thanks for reply.
 

you never declare what M,N are in the testbench.
 

Dear permute,

I declare M,N as an integer in the testbench. But, this error occur:

Error (10465): VHDL error at transpose_tb.vhd(17): name "M" cannot be used because it is already used for a previously declared item.

Thanks for reply.

---------- Post added at 08:39 ---------- Previous post was at 06:56 ----------

Dear all,

I have declare M,N in the testbench as follow:
signal M:integer :=3;
signal N:integer :=3;

Know I get another error:
Error (10517): VHDL type mismatch error at transpose_tb.vhd(38): matrix type does not match integer literal.
Can anyone help me.Many thanks.
 

you cannot use M and N as signals, they have to be declared as constant or generics.
 

Dear TrickyDicky,

I have write generic (M: integer :=3; N: integer :=3); in testbench as I show at my first post. But, the error said that I not declare M and N.
Then when I declare the M and N for the port another error occures said M,N already used for previously declared items.
Can you tell me what Iam wrong? Thanks for reply.
 

M and N are not delcared in your testbench. They are declared as part of a compoenent, which means they are NOT visible in the testbench. They need to be declared inside the entity (as a generic on the Testbench) or inside the architectre (at the top!).
 

Dear TrickyDicky,

I declare M,N inside the architecture (at the top) like below:

architecture bench of transpose_tb is
generic (M: integer :=3;
N: integer :=3);

component transpose
generic (M: integer :=3;
N: integer :=3);
port (x: in matrix (0 to M-1, N-1 downto 0);
y: out matrix (0 to M-1, N-1 downto 0);
clk: in bit);
end component;

Is it what do you mean?Sorry too much questions.I try that but still error.Thanks for reply.
 

No, you cannot put generics inside an architecture. They have to be delcared as part of the entity:

Code:
entity transpose_TB is
  generic (M: integer :=3;
  N: integer :=3);
end entity transpose_TB;

or as constants inside the architecture:

Code:
architecture bench of transpose_TB is
  constant N, M : integer := 3;
begin

.....
 
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    fanwel

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Dear TrickyDicky,

I write the second code in the testbench and its okay. But, another error at line 38 occured;
--line 38
x <= (12,9);

Error (10517): VHDL type mismatch error at transpose_tb.vhd(38): matrix type does not match integer literal.
Is that the way I write the input test is wrong?Many thanks.
 

Dear TrickyDicky,

This is the main code:

---------package---------
package my_data_types is
type matrix is array (natural range<>, natural range<>) of integer;
end package my_data_types;

----------main code-------
use work.my_data_types.all;

entity transpose is
generic (M: integer :=3;
N: integer :=3);
port (x: in matrix (0 to M-1, N-1 downto 0);
y: out matrix (0 to M-1, N-1 downto 0);
clk: in bit);
end transpose;

architecture transpose of transpose is
begin
process(clk)
begin
if (clk'event and clk='1') then
for i in 0 to M-1 loop
for j in 0 to M-1 loop
y(i,j) <= x(j,i);
end loop;
end loop;
end if;
end process;
end transpose;

This is the testbench:

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
use work.my_data_types.all;

entity transpose_tb is
end;

architecture bench of transpose_tb is
constant M,N: integer :=3;

component transpose
generic (M: integer :=3;
N: integer :=3);
port (x: in matrix (0 to M-1, N-1 downto 0);
y: out matrix (0 to M-1, N-1 downto 0);
clk: in bit);
end component;

signal x: matrix (0 to M-1, N-1 downto 0);
signal y: matrix (0 to M-1, N-1 downto 0);
signal clk: bit;

constant clock_period: time := 10 ns;
signal stop_the_clock: boolean;

begin

uut: transpose generic map ( M => 3,
N => 3 )
port map ( x => x,
y => y,
clk => clk );

stimulus: process
begin
x <= (12,9);
wait for 150ns;

stop_the_clock <= true;
wait;
end process;

clocking: process
begin
while not stop_the_clock loop
clk <= '1', '0' after clock_period / 2;
wait for clock_period;
end loop;
wait;
end process;

end;
 

the problem is this line, as you highlighted:

x <= (12, 9);

X is declared as a 3x3 matrix, but you have only attempted to input 2 values (instead of the required 9).

You need to specify it like this:

x <= ( (0,1,2), (3,4,5), (6,7,8) ); --3 lots of 3 values
 
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    fanwel

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Dear TrickyDicky,

Thank you very much. Really help me solve this problem.
Many thanks.
 

Dear all,

I try to have 8x8 matrix by change the code generic M,N: integer:=8. But this error occured:

Error: Design requires 4097 I/O resources -- too many to fit in 634 available in the selected device or any device in the device family.
How can i overcome this problems?
 

three options:
1. Make the matrix smaller
2. Get a bigger device.
3. Realise that a matrix transpose does not require any registers because it is simpy a placement of all values, so registers are not required for it.
 

this occurs when you leave automatic IO insertion (synthesis option) turned on. it is trying to synthesize to an actual FPGA, but to do so it needs to find actual pins on the device. you quickly run out of pins. when io insertion is turned off, the tools no longer connect anything to the FPGA pins.
 

Dear TrickyDicky,

In you third option, it is when I not used a register I can simulate for 8x8 matrix?
Actually I want to have 8x8 matrix transpose. Many thanks.
 

Ok, I misread your error. But it shows you are not quit thinking in terms of hardware, Are you from a software background?

Your compiler should have the option to give you virtual pins if this is just a test compile. The compiler has to connect each bit to a seperate IO pin, and with virtual pins you are telling it that you do not want to connect this block to the IOs yet, you're just running it through as a test. If you did mean to connect it to the pin IOs, you will have to follow options 1 or 2, but I wonder where all this data is going to come from. I CPU is not going to provide you with so much parrallel data.

And as a note on transpose - this again makes me think you're a software guy. In hardware, a matrix transpose can be done for free.
 

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