Test Scenarios of DDR2 controller

[sumathi0809]

Please anybody tell me, what will be the "test scenarios for verification of DDR2 controller"..?

 

[sharath666]

1)DDR initialization
2)Memory writes and reads
3)Scenario 2) for different combinations of rows, columns and banks
4)Power down(Both precharge and active)
5)Refresh operation

 

[sumathi0809]

Thank you for your reply, if possible can u tell me how to verify refresh, controller-PHY will automatically performs refresh operation do i have to poll for PHY refresh command to memory at periodic intervals..?

 

[sharath666]

If there is a refresh violation, the memory model itself throws out an error and the simulation stops. But it will not warn you if the time is in excess. Use a simulator to determine the exact delay and refer the memory datasheet to confirm the same.